The smallest and most advanced chips currently commercially available are made up of transistors with gates about 10 nm long, but IBM has now unveiled plans to cut them in half. To create 5 nm chips, the company is ditching the standard FinFET architecture in favor of a new structure built with a stack of four nanosheets, allowing some 30 billion transistors to be packed onto a chip the size of a fingernail and promising significant gains in power and efficiency.
First coined in the 1970s, Moore’s Law was the observation that the number of transistors on a single chip would double every two years. The trend has held up pretty well ever since, but the time frame of the doubling has slowed down a little in recent years. In consumer electronics, 14 nm chips are still stock-standard, but advances from the likes of Intel and Samsung mean that 10 nm versions have started hitting the high-end market.
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